The present invention relates to a semiconductor device equipped with a MISFET-controlled thyristor consuming less power in a gate circuit and exhibiting excellent switching characteristics. This is a power semiconductor device capable of controlling large currents under a high withstand voltage.
A power semiconductor that can control large currents under a high withstand voltage must have a low potential drop or a low on-state voltage under a current conduction, and furthermore, must be capable of turning a current on and off rapidly, that is, high-speed switching. To meet these requirements, an insulting gate bipolar transistor (IGBT) with lower on-state voltage than a power MOSFET, and capable of higher speed switching than a bipolar transistor must be developed. Furthermore, it is also necessary to develop a semiconductor device which can control a thyristor using a MOS gate with low on-sate voltage.
FIG. 5 shows a cross section of a MOS-controlled thyristor element capable of suppressing power consumption in a gate current when turned off, as well as high-speed switching. This element is called an emitter-switched thyristor (hereinafter EST).
FIG. 5 shows a vertical-type thyristor element, which uses a substrate (10) made of a thin silicon sheet consisting of a p.sup.+ -type anode layer (12) disposed on a metallic anode electrode (11), an N-type guard layer (13) laminated on the anode layer (12), and an N.sup.- -type base layer (14) laminated on the N-type guard layer (13). On the surface of the N.sup.- -type base layer (14) on the substrate (10), a P-type base layer (15) is formed, and on the surface of the P-type base layer (15), an N.sup.+ -type source layer (17) and a floating emitter layer (16) are formed. Furthermore, a polysilicon layer to be used as a first gate electrode (21) and a second gate electrode (22) is formed via a gate-insulating film (18). The source layer (17) and the floating emitter layer (16) are shallower than the P-type base layer (15), and an N-channel type first MOS (35) is made up of a first gate electrode (21), the source layer (17) and the floating emitter (16). An N-channel second MOS (36) is made up of the second gate electrode (22), the floating emitter layer (16) and the N.sup.- -type base layer (14). Numerals (35') and (36') show channel regions of the first and second MOS (35) and (36), respectively. These gate electrodes (21, 22) are driven by the same gate potential. The source layer (17) is made to contact with the emitter electrode (19) so that it short-circuited with the P-type base layer (15). Many thyristor elements are constructed on the surface of the semiconductor device by such first and second MOS (35 and 36), and the emitter electrode (19).
In the above element, an NPN-type transistor (31) is formed by the N.sup.+ -type floating emitter layer (16), the P-type base layer (15), the N.sup.- -type base layer (14) and the N-type guard layer (13). In addition, a PNP-type transistor (32) is formed by the P-type base layer (15), the N.sup.- -type base layer (14), the N-type guard layer (13) and the P.sup.+ -type anode layer (12). In other words, the thyristor element is constructed by the N.sup.+ -type floating emitter layer (16), the P-type base layer (15), the N.sup.- -type base layer (14), the N-type guard layer (13) and the P.sup.+ -type anode layer (12).
In this element, the first and second MOS (35, 36) are turned on when a positive potential is applied to the gate electrodes (21, 22). As a result, a current flows into the base of the PNP-type transistor (32), thus the entire element is conducted. The PNP-type transistor is now in the same condition as the IGBT. As the base short circuit current that flows from the emitter electrode (19) into the base layer (15) increases, the base potential at the NPN transistor (31) rises by a base short circuit resistance (39) to this current. Therefore, this NPN transistor (31) is also conducted, as does the thyristor consisting of the transistors (31, 32). The base short circuit resistance (39) works as a result of the P-type base layer (15), and the current flowing in the base layer (15) raises the potential at the base layer (15) directly below the emitter layer (16), and conducts the NPN transistor (31).
FIG. 7 shows the voltage-current characteristics of this element. As described above, this element moves to a thyristor mode (52) through an IGBT mode (51). A sharp decrease in the resistance that occurs during the transference from the IGBT mode (51) to the thyristor mode (52) causes the voltage to decrease, thereby resulting in a discontinuity point (53).
To turn this element off, it is sufficient to apply a zero or negative potential to the gate electrodes (21, 22). This application turns the MOS (35, 36) off, while the emitter layer (16) is insulated from the emitter electrode (19), and the element is turned off. Thus, the emitter layer (16) is switched by the MOS (35), thereby enabling high-speed switching. The N.sup.- -type base layer (14) is used to suppress the on-state voltage, and N-type guard layer (13) is used to suppress the spread of the depletion layer and raise the withstand potential.
Because of the capability of such a MOS controlled thyristor element, which is low in the on-state voltage and is capable of high-speed switching, it has drawn attention as a power semiconductor. However, there are problems to be solved for this element, such as how to decrease the resistance in the first MOS (35), how to reduce the element resistance, how to obtain continuous voltage-current curve, how to reduce an on-state resistance by providing the thyristor operation at an early stage, and how to prevent a latch-up phenomenon caused by parasitic thyristors to raise the controllable current values.
First, for the first MOS which performs a switching operation for the floating emitter layer, since the first MOS is connected to the thyristor in series, there is a problem that the resistance of the entire element can not be reduced unless the resistance in the first MOS is reduced even if the resistance on the thyristor side is decreased. To reduce the resistance in the first MOS, it is necessary to shorten the channel length of the MOS, and furthermore micro-processing must be performed on the impurity layer that is a part of the MOS, and on the polysilicon layer which constitutes a gate electrode. Unfortunately, reducing the channel length aggravates the element characteristics because it leads to a decreased source-drain withstand voltage in the MOS.
In the conventional MOS-controlled thyristor as described above, discontinuity point in the current-voltage curve occurs during the transfer from the IGBT mode to the thyristor mode. If a circuit is constructed using this element, it may generate a trouble such as noise that is attributable to the occurrence of this discontinuity.
Furthermore, in a conventional MOS-controlled thyristor, because the P-type base layer is connected to the emitter electrode, a current flows from the base layer to the emitter electrode. Therefore, the injection of electrons from the emitter layer is suppressed, thereby making it difficult to realize the thyristor mode at an early stage. Therefore, reducing on-state resistance is difficult.
In this MOS-controlled thyristor, an NPN-type transistor (33) is parasitic as indicated by the broken lines in FIG. 6, as a result of the N.sup.+ -type source layer (17), the P-type base layer (15), the N.sup.- -type base layer (14) and the N-type guard layer (13). Therefore, when the current is increased and this parasitic transistor (33) is turned on, a latch-up condition is caused wherein the thyristor formed by the transistors (33, 32) is conducted, and current control becomes impossible. For this reason, the upper limit of a current that can be controlled by this element is limited to a range in which no latch-up condition occurs. Particularly, because the potential in the P-type base layer directly below the emitter layer has been high when the conventional MOS-controlled thyristor is turned on, concentrations of the minority carriers are high. Moreover, since the minority carriers are concentrated on the base layer directly below the source layer, the latch-up is liable to occur.
Therefore, in the light of the above problems, the present invention is intended to provide, by using a laminated floating emitter layer and a base layer, a semiconductor device that has a thyristor with a low-resistance, a high-withstand voltage, continuous voltage-current characteristics and a high upper limit of controllable currents.